Phase lock loops (PLLs) are well known in the field of electronics. Their function is to provide an output signal which is locked to the frequency of an input signal. Such `locking` is achieved by using amongst other things a phase detector which compares the phase of the input signal with that of the signal generated by the PLL.
U.S. Pat. No. 4,771,249 discloses a PLL circuit comprising a phase detector having fast start up capability and stable operating characteristics. In this circuit, a reference clock is compared with a clock generated by the PLL. Control signals are generated by the phase detector having a pulse width proportional to the phase difference between the two clocks. If a falling edge of the reference clock precedes the PLL generated clock, a signal UP is generated. The UP signal is negated by a falling edge of the PLL generated clock. If a falling edge of the PLL generated clock precedes the reference clock, a signal DOWN is generated. The DOWN signal is negated by a falling edge of the reference clock.
Each time an UP signal is generated, an input signal COUNT of a T-type flip-flop is set. Each time a DOWN signal is generated, the signal COUNT is reset. A counter which counts up to a predetermined number of UP-DOWN transitions is formed by coupling a plurality of these T-type flip-flops together, the predetermined number of transitions depending on the number of flip-flops used. If there is a very large frequency shift between the reference clock and the PLL generated clock, the counter is reset. Once the counter reaches the predetermined count, it is assumed that lock has been achieved. A LOCK signal is then asserted and the chip incorporating the PLL commences normal operation.
Fig. 1 shows how the frequency of a PLL generated signal changes as the PLL attempts to lock to the reference signal for an overdamped loop and an underdamped loop. Curve A represents an underdamped loop and curve B represents an overdamped loop.
For the underdamped loop (curve A), the PLL counter counts the UP-DOWN transitions. If the count is completed at time X, then the asserted LOCK signal correctly indicates that lock has been achieved. However, if the count is completed at time Y, the loop is not locked and the asserted LOCK signal falsely indicates that lock has been achieved. Thus, for severely underdamped loops, the prior art PLL suffers from a problem of inaccurate lock detection.
For the overdamped loop (curve B), no UP-DOWN transitions occur so that the prior art PLL circuit cannot detect lock for a PLL in this state. In loops that are overdamped, it has been difficult devising a mechanism that detects the lock state in a timely and reliable manner. In extremely overdamped PLLs, lock notification does not occur so that chips with overdamped PLLs are normally discarded as faulty.
The prior art PLL circuits also suffer from problems arising during the locking process due to production tolerances. The production tolerances cannot be controlled by the chip designer.
There is therefore a significant need for a PLL which can detect lock for both overdamped and underdamped states and can operate in an optimal fashion irrespective of process variations and tolerances.